Traditional techniques of manufacturing semiconductor devices and packages, wherein layers are built sequentially one on top of another, suffer several drawbacks. For example, layers requiring higher annealing temperature would have to be manufactured before those requiring lower annealing temperature, thereby imposing several limitations upon the design and packaging of devices.
Sequentially building of layers under traditional techniques also has low overall yield. For example, if yield in the manufacture of one layer is 90% and yield in the manufacture of another layer is 90%, the average overall yield would at most be 81%.
If a semiconductor device can be divided into separate layers that are capable of being manufactured and tested individually, drawbacks including those identified above are circumvented. For example, two layers requiring different annealing temperatures can be manufactured individually and then combined into a final product. Moreover, as devices are formed by combining only those layers have already been tested, overall yield will be limited only by the yield of the assembling step, and should thus even be higher than 90%.
Furthermore, as individual layers can be manufactured and tested in parallel, manufacturing time of a device is shortened.